Sigma-Delta modulators may be used for implementing radiofrequency (RF) receivers in many different types of wireless telecommunication devices. These wireless telecommunication devices may be used for example for several applications such as Software Defined Radio (SDR), Cognitive Radio (CR), Internet of Things (IoT) and Base Stations or cellular phones. These wireless telecommunication devices have for example to comply with different wireless telecommunication standards, including GSM/GPRS, EDGE, UMTS, LTE, Wi-Fi, ZigBee, Bluetooth, etc, and thus have to be able to convert analog input signals having various frequency ranges.
FIG. 1 is a schematic representation of an embodiment of a highly digitized RF receiver 100. The RF receiver 100 comprises an antenna 5, an amplifier 10 (LNA, Low Noise Amplifier), an RF Analog-to-Digital Converter (ADC) 11, a first in-phase branch mixer 12, a first in-phase branch decimation filter 13, a digital signal processor (DSP) 14, an Numerically
Controlled Oscillator (NCO) 15, a phase shifter 16 for producing a phase shift of π/2, a second quadrature branch mixer 17, a second quadrature branch decimation filter 18. The NCO 15 generates a sinusoidal signal at center frequency f0 which is used by each of the two mixers 12, 17 for down-converting the output of the ADC 11. In this embodiment, the ADC 11 is close to the antenna 5 and follows directly the LNA 10. In this case, most of the signal processing functions—including down-conversion mixers as well as filtering and channel selection—are implemented in the easily programmable digital domain: it is then easier to reconfigure the RF receiver when switching from one standard to another. This kind of receiver is commonly known as highly digitized SDR receiver.
In this embodiment, the Analog to Digital Converter (ADC) is a Sigma-Delta ADC (referred to herein as ΣΔ ADC). AΣΔ ADC is a loop circuit that comprises a forward path and a feedback path for generating at least one feedback signal feeding the forward path.
FIG. 2 is a schematic representation of an embodiment of a ΣΔ ADC 200 including a loop with a forward path and a feedback path. The loop comprises a loop filter including one or more subfilters 210, 230 and one or more Digital to Analog Converters (DACs) 251, 252, 253. The forward path comprises a first subfilter 230, a second subfilter 210 and a quantizer 220. The first subfilter 230 is applied to the difference between the analog input signal 201 and the first feedback signal 203 and generates a filtered difference signal 231. The second subfilter 210 is applied to the filtered difference signal 231 generated by the first subfilter 230 and generates a filtered signal 211. The adder 240 generates a difference signal 241 from the filtered signal 211 and the feedback signal 204. The order of the loop filter may be increased by adding more subfilters between the subfilter 210 and the adder 240. The quantizer 220 generates a digital output signal 222 at the sampling frequency fs from the difference signal 241. Due to the time delay, tq, resulting from the quantizer 220 response-time, the digital output signal 222 is delayed compared to the analog input signal 201. This time delay is usually referred to as the ΣΔ loop delay, td. The feedback path comprises several DACs 251, 252, 253, for generating respectively the feedback signals 203, 204, 205 feeding the forward path. The coefficients of the DACs 251, 252, 253 are noise shaping coefficients for shaping the quantification noise. While FIG. 2 shows a ΣΔ ADC using feedback noise shaping coefficients, the same principles can be applied to a ΣΔ ADC using feedforward and/or feedback noise shaping coefficients. The noise-shaping coefficients may also be implemented using an FIR-DACs comprising a FIR (Finite Impulse Response) filter.
In order to adapt to the requirements of different wireless communication standards, the ΣΔ ADC should be tunable to be able to process analog input signals that have different bandwidths BW and/or different center frequencies f0. A tunable ΣΔ ADC may be implemented as a low-pass ΣΔ ADC or a band-pass ΣΔ ADC. In a tunable low-pass ΣΔ ADC, the loop filter is a low-pass filter whose bandwidth is tunable. In a tunable band-pass ΣΔ ADC, the loop filter is a band-pass filter whose both the center frequency f0 and the bandwidth are tunable, In both cases, the noise shaping coefficients of the loop filter have to be determined such that the Noise Transfer Function (NTF) of the ΣΔ ADC has a given shape and matches the desired bandwidth BW and/or the desired center frequency f0. See for example the document published 2002, entitled “H. Aboushady and M. M. Louerat, “Systematic Approach for Discrete-Time to Continuous-Time Transformation of Sigma-Delta Modulators”, by Aboushady et al, IEEE International Symposium on Circuits and Systems, ISCAS'02, Phoenix Ariz., USA, May 2002.”
The performances of this ΣΔ ADC may be improved for example by using either higher order for the loop filter, by increasing the Oversampling Ratio (OSR=fs/2BW) and/or by increasing the number of bits of the quantizer, thus using multi-bit quantizer.
FIGS. 3A-3C illustrate the shape of power spectral density (PSD) of the quantization noise as a function of the frequency for a respective center frequency f01, f02, f03 of the analog input signal. The sampling frequency being noted fs, the frequency range of interest is [0, fs/2]. The desired frequency band 300A, 300B, 300C of the analog input signal is assumed to be centered around the respective center frequencies f01, f02, f03. Those curves illustrate the fact, that when the center frequency varies, the shape of the power spectral density (PSD) of the quantization noise also varies. As a consequence, the center frequency of the subfilters of the tunable ΣΔ ADC have to be tuned in order to suppress the quantization noise around the desired center frequency.
In addition, the stability of the tunable ΣΔ ADC at each desired center frequency f0/bandwidth have to be controlled by a proper adjustment of the noise shaping coefficients of the loop filter and of the subfilters.
Example embodiments of a ΣΔ ADC are disclosed for example in patent document U.S. Pat. No. 6,693,573 B1, by Linder et al. In these embodiments, the Micro Electro Mechanical System (MEMS) technology is used, including LC resonators with high quality factor. The center frequency or the tuning range of this ΣΔ ADC may be changed by tuning the capacitance of the LC resonators. The ΣΔ ADC works with a center frequency around 1 GHz-2 GHz.
Another example is described in the document entitled “A DC-to-1 GHz Tunable RF ΣΔ ADC Achieving DR=74 dB and BW=150 MHz at f0=450 MHz using 550 mW” by
Shibata et al, IEEE Journal of solid-state circuits, vol. 47, N° 12, December 2012, describes a modulator having a tuning range from 0-to-1 GHz and consuming 750 mW.
The tuning of these ΣΔ ADCs is quite complex and due to this complexity, the tuning range may be limited. Adapting those modulators for higher frequencies would thus imply a higher complexity, higher power consumption and higher size for the ΣΔ ADC circuit. As a consequence, such ΣΔ ADCs could not be used for a wide variety of applications or would not be small enough for being integrated in small and compact wireless telecommunication devices.
There is therefore a need for a simple tunable ΣΔ ADC, of small size and low power consumption suitable for converting analog input signals having various frequency bands.